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International Conference on Parallel Computing in Electrical Engineering (PARELEC'02)
Modeling Parallel program Execution Control by Directed Graphs with Synchronous Communication
Warsaw, Poland
September 22-September 25
ISBN: 0-7695-1730-7
ASCII Text
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Damian Kopanski, Eryk Laskowski, Marek Tudruj, "Modeling Parallel program Execution Control by Directed Graphs with Synchronous Communication," Parallel Computing in Electrical Engineering, International Conference on, pp. 76, International Conference on Parallel Computing in Electrical Engineering (PARELEC'02), 2002.
 
 
BibTex
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@article{ 10.1109/PCEE.2002.1115205,
author = {Damian Kopanski and Eryk Laskowski and Marek Tudruj},
title = {Modeling Parallel program Execution Control by Directed Graphs with Synchronous Communication},
journal ={Parallel Computing in Electrical Engineering, International Conference on},
volume = {0},
year = {2002},
isbn = {0-7695-1730-7},
pages = {76},
doi = {http://doi.ieeecomputersociety.org/10.1109/PCEE.2002.1115205},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Parallel Computing in Electrical Engineering, International Conference on
TI - Modeling Parallel program Execution Control by Directed Graphs with Synchronous Communication
SN - 0-7695-1730-7
SP
EP
A1 - Damian Kopanski,
A1 - Eryk Laskowski,
A1 - Marek Tudruj,
PY - 2002
KW - null
VL - 0
JA - Parallel Computing in Electrical Engineering, International Conference on
ER -
 
Damian Kopanski, Polish-Japanese Institute of Information Technology
Eryk Laskowski, Polish Academy of Sciences
Marek Tudruj, Polish Academy of Sciences

The problem of graph modeling of parallel program execution control for the use of symbolic graph simulation facilities is discussed in the paper. This problem has become more important recently, as there is a need for homogenous, symbolic representation of a parallel program and system hardware.

The paper presents a method and a new software tool that provide automated extending parallel program graphs by sub-graphs insertions. The inserted sub-graphs represent the execution control of program and the behavior of the system hardware. The tool consists of the graph execution simulator and a special graph specification language based on the XML syntax. They both establish an environment for synthetic parallel program graph execution time evaluation in parallel systems with definable program execution paradigms.

Citation:
Damian Kopanski, Eryk Laskowski, Marek Tudruj, "Modeling Parallel program Execution Control by Directed Graphs with Synchronous Communication," parelec, pp.76, International Conference on Parallel Computing in Electrical Engineering (PARELEC'02), 2002
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