Square Interconnection Network for Data Permutation

P
PARELEC
2002
International Conference on Parallel Computing in Electrical Engineering (PARELEC'02)
Abstract - Square Interconnection Network for Data Permutation

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	Similar Articles Articles by Zbigniew Kokosiński

International Conference on Parallel Computing in Electrical Engineering (PARELEC'02)

Warsaw, Poland

September 22-September 25

ISBN: 0-7695-1730-7

	ASCII Text	x
	Zbigniew Kokosiński, "Square Interconnection Network for Data Permutation," Parallel Computing in Electrical Engineering, International Conference on, pp. 44, International Conference on Parallel Computing in Electrical Engineering (PARELEC'02), 2002.

	BibTex	x
	@article{ 10.1109/PCEE.2002.1115195, author = {Zbigniew Kokosiński}, title = {Square Interconnection Network for Data Permutation}, journal ={Parallel Computing in Electrical Engineering, International Conference on}, volume = {0}, year = {2002}, isbn = {0-7695-1730-7}, pages = {44}, doi = {http://doi.ieeecomputersociety.org/10.1109/PCEE.2002.1115195}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Parallel Computing in Electrical Engineering, International Conference on TI - Square Interconnection Network for Data Permutation SN - 0-7695-1730-7 SP EP A1 - Zbigniew Kokosiński, PY - 2002 KW - null VL - 0 JA - Parallel Computing in Electrical Engineering, International Conference on ER -

Zbigniew Kokosiński, Cracow University of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PCEE.2002.1115195

In this paper a square cellular network for data permutation in a SIMD model is described. It has n²/4 2-permuters only, and realizes an arbitrary permutation pattern in two passes. For this network a programming algorithm is provided with O(n) sequential time complexity. Due to its regular cellular structure the square network is suitable for VLSI implementation.

Citation:

Zbigniew Kokosiński, "Square Interconnection Network for Data Permutation," parelec, pp.44, International Conference on Parallel Computing in Electrical Engineering (PARELEC'02), 2002

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