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International Conference on Parallel Computing in Electrical Engineering (PARELEC'00)
Parallel CLA Algorithm for Fast Addition
Quebec, Canada
August 27-August 30
ISBN: 0-7695-0759-X
ASCII Text
x 
 
Mahmoud A. Manzoul, "Parallel CLA Algorithm for Fast Addition," Parallel Computing in Electrical Engineering, International Conference on, pp. 55, International Conference on Parallel Computing in Electrical Engineering (PARELEC'00), 2000.
 
 
BibTex
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@article{ 10.1109/PCEE.2000.873601,
author = {Mahmoud A. Manzoul},
title = {Parallel CLA Algorithm for Fast Addition},
journal ={Parallel Computing in Electrical Engineering, International Conference on},
volume = {0},
year = {2000},
isbn = {0-7695-0759-X},
pages = {55},
doi = {http://doi.ieeecomputersociety.org/10.1109/PCEE.2000.873601},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Parallel Computing in Electrical Engineering, International Conference on
TI - Parallel CLA Algorithm for Fast Addition
SN - 0-7695-0759-X
SP
EP
A1 - Mahmoud A. Manzoul,
PY - 2000
VL - 0
JA - Parallel Computing in Electrical Engineering, International Conference on
ER -
 
Mahmoud A. Manzoul, American University of Sharjah
The Carry Look-Ahead (CLA) is a popular addition algorithm in the Arithmetic and Logic Unit (ALU) of computers. The algorithm is based on the computation of the carries using one CLA circuit. In the paper, a parallel version of the CLA circuit will be presented. Two, three or four parallel CLA circuits may be employed in the computation of the carries. The computations of the carries are equally divided among the parallel CLA circuits. Despite the inclusion of non-binary logic, the presented parallel algorithm is completely realizable by binary gates. The different versions of the parallel CLA algorithm and the conventional CLA algorithm are compared in term of gate delays.
Citation:
Mahmoud A. Manzoul, "Parallel CLA Algorithm for Fast Addition," parelec, pp.55, International Conference on Parallel Computing in Electrical Engineering (PARELEC'00), 2000
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