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International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06)
Time Domain Decomposition in Parallel Analysis of Transient States
Bialystok, Poland
September 13-September 17
ISBN: 0-7695-2554-7
ASCII Text
x 
 
Jaroslaw Forenc, "Time Domain Decomposition in Parallel Analysis of Transient States," Parallel Computing in Electrical Engineering, International Conference on, pp. 295-300, International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06), 2006.
 
 
BibTex
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@article{ 10.1109/PARELEC.2006.82,
author = {Jaroslaw Forenc},
title = {Time Domain Decomposition in Parallel Analysis of Transient States},
journal ={Parallel Computing in Electrical Engineering, International Conference on},
volume = {0},
year = {2006},
isbn = {0-7695-2554-7},
pages = {295-300},
doi = {http://doi.ieeecomputersociety.org/10.1109/PARELEC.2006.82},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Parallel Computing in Electrical Engineering, International Conference on
TI - Time Domain Decomposition in Parallel Analysis of Transient States
SN - 0-7695-2554-7
SP295
EP300
A1 - Jaroslaw Forenc,
PY - 2006
KW - null
VL - 0
JA - Parallel Computing in Electrical Engineering, International Conference on
ER -
 
Jaroslaw Forenc, Bialystok Technical University, Poland
In this paper the parallel method for the transient state analysis in electrical circuits, described by a system of ordinary differential equations, is presented. The general idea of this method is based on decomposition of the analyzed time domain into sub-intervals. Parallel computations in particular sub-intervals of time are conducted with the initial conditions determined on the basis of an approximation of convergent graph solution by exponential function and with the use of sequential numerical Runge-Kutta method.
Citation:
Jaroslaw Forenc, "Time Domain Decomposition in Parallel Analysis of Transient States," parelec, pp.295-300, International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06), 2006
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