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International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06)
Speeding Up Sequential Simulated Annealing by Parallelization
Bialystok, Poland
September 13-September 17
ISBN: 0-7695-2554-7
ASCII Text
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Zbigniew J. Czech, "Speeding Up Sequential Simulated Annealing by Parallelization," Parallel Computing in Electrical Engineering, International Conference on, pp. 349-356, International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06), 2006.
 
 
BibTex
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@article{ 10.1109/PARELEC.2006.74,
author = {Zbigniew J. Czech},
title = {Speeding Up Sequential Simulated Annealing by Parallelization},
journal ={Parallel Computing in Electrical Engineering, International Conference on},
volume = {0},
year = {2006},
isbn = {0-7695-2554-7},
pages = {349-356},
doi = {http://doi.ieeecomputersociety.org/10.1109/PARELEC.2006.74},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Parallel Computing in Electrical Engineering, International Conference on
TI - Speeding Up Sequential Simulated Annealing by Parallelization
SN - 0-7695-2554-7
SP349
EP356
A1 - Zbigniew J. Czech,
PY - 2006
KW - Parallel simulated annealing
KW - bicriterion optimization
KW - vehicle routing problem with time windows
VL - 0
JA - Parallel Computing in Electrical Engineering, International Conference on
ER -
 
Zbigniew J. Czech, Silesia University of Technology, Poland
A parallel algorithm of simulated annealing to solve the vehicle routing problem with time windows (VRPTW) is considered. The VRPTW is an NP-hard bicriterion optimization problem in which both the number of vehicles and the total distance traveled by vehicles are minimized. The objective is to establish to what extent the computation time required to solve the VRPTWcan be decreased by a number of co-operating parallel processes with no loss of quality of solutions. The quality of a solution is meant as its proximity to the optimum (or best known) solution. Furthermore, some factors are proposed which allow to rank the VRPTW benchmarking tests according to their difficulties.
Index Terms:
Parallel simulated annealing, bicriterion optimization, vehicle routing problem with time windows
Citation:
Zbigniew J. Czech, "Speeding Up Sequential Simulated Annealing by Parallelization," parelec, pp.349-356, International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06), 2006
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