Mapping DSP Algorithms into FPGA

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	Similar Articles Articles by Oleg Maslennikow Articles by Anatolij Sergiyenko

International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06)

Bialystok, Poland

September 13-September 17

ISBN: 0-7695-2554-7

	ASCII Text	x
	Oleg Maslennikow, Anatolij Sergiyenko, "Mapping DSP Algorithms into FPGA," Parallel Computing in Electrical Engineering, International Conference on, pp. 208-213, International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06), 2006.

	BibTex	x
	@article{ 10.1109/PARELEC.2006.51, author = {Oleg Maslennikow and Anatolij Sergiyenko}, title = {Mapping DSP Algorithms into FPGA}, journal ={Parallel Computing in Electrical Engineering, International Conference on}, volume = {0}, year = {2006}, isbn = {0-7695-2554-7}, pages = {208-213}, doi = {http://doi.ieeecomputersociety.org/10.1109/PARELEC.2006.51}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Parallel Computing in Electrical Engineering, International Conference on TI - Mapping DSP Algorithms into FPGA SN - 0-7695-2554-7 SP208 EP213 A1 - Oleg Maslennikow, A1 - Anatolij Sergiyenko, PY - 2006 KW - null VL - 0 JA - Parallel Computing in Electrical Engineering, International Conference on ER -

Oleg Maslennikow, Technical University of Koszalin, Poland

Anatolij Sergiyenko, National Technical University of Ukraine, Ukraine

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PARELEC.2006.51

A method of mapping DSP algorithms into FPGA devices is considered. Algorithms are represented by synchronous data flow graphs, and are mapped into pipelined data path. The method consists of placing the algorithm graph in the multidimensional index space and mapping it into structure and event subspaces. The special limitations, which are injected to the mapping process, minimize both clock time and hardware volume including multiplexer inputs.

Citation:

Oleg Maslennikow, Anatolij Sergiyenko, "Mapping DSP Algorithms into FPGA," parelec, pp.208-213, International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06), 2006

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