Generalised Resource Model for Parallel Instruction Scheduling

P
PARELEC
2006
International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06)
Abstract - Generalised Resource Model for Parallel Instruction Scheduling

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International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06)

Bialystok, Poland

September 13-September 17

ISBN: 0-7695-2554-7

	ASCII Text	x
	Jan M?, "Generalised Resource Model for Parallel Instruction Scheduling," Parallel Computing in Electrical Engineering, International Conference on, pp. 89-94, International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06), 2006.

	BibTex	x
	@article{ 10.1109/PARELEC.2006.40, author = {Jan M?}, title = {Generalised Resource Model for Parallel Instruction Scheduling}, journal ={Parallel Computing in Electrical Engineering, International Conference on}, volume = {0}, year = {2006}, isbn = {0-7695-2554-7}, pages = {89-94}, doi = {http://doi.ieeecomputersociety.org/10.1109/PARELEC.2006.40}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Parallel Computing in Electrical Engineering, International Conference on TI - Generalised Resource Model for Parallel Instruction Scheduling SN - 0-7695-2554-7 SP89 EP94 A1 - Jan M?, PY - 2006 KW - null VL - 0 JA - Parallel Computing in Electrical Engineering, International Conference on ER -

Jan M?, Dresden University of Technology, Germany

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PARELEC.2006.40

In this paper we introduce a generalised resource model for parallel instruction scheduling. This model is used to formulate the resource constraints for periodic loop schedules, which are then rewritten employing an efficient flow graph model.

The generalisation leads to a significant simplification and acceleration of the painful process of modelling new resource classes, and of incorporating specific processor features. Moreover, the model grants an accurate representation of the processor resources. We illustrate these properties at the examples of functional units and processor registers.

Citation:

Jan M?, "Generalised Resource Model for Parallel Instruction Scheduling," parelec, pp.89-94, International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06), 2006

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