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International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06)
Derivation of Packing Instructions for Exploiting Sub-Word Parallelism
Bialystok, Poland
September 13-September 17
ISBN: 0-7695-2554-7
ASCII Text
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Rainer Schaffer, Renate Merker, Francky Catthoor, "Derivation of Packing Instructions for Exploiting Sub-Word Parallelism," Parallel Computing in Electrical Engineering, International Conference on, pp. 167-172, International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06), 2006.
 
 
BibTex
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@article{ 10.1109/PARELEC.2006.28,
author = {Rainer Schaffer and Renate Merker and Francky Catthoor},
title = {Derivation of Packing Instructions for Exploiting Sub-Word Parallelism},
journal ={Parallel Computing in Electrical Engineering, International Conference on},
volume = {0},
year = {2006},
isbn = {0-7695-2554-7},
pages = {167-172},
doi = {http://doi.ieeecomputersociety.org/10.1109/PARELEC.2006.28},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Parallel Computing in Electrical Engineering, International Conference on
TI - Derivation of Packing Instructions for Exploiting Sub-Word Parallelism
SN - 0-7695-2554-7
SP167
EP172
A1 - Rainer Schaffer,
A1 - Renate Merker,
A1 - Francky Catthoor,
PY - 2006
KW - null
VL - 0
JA - Parallel Computing in Electrical Engineering, International Conference on
ER -
 
Rainer Schaffer, Dresden University of Technology, Germany
Renate Merker, Dresden University of Technology, Germany
Francky Catthoor, IMEC, Belgium
Today the presence of sub-word parallelism (SWP) is quite general in several architectures such as in general purpose processors or in the functional units of connected processing elements of application specific architectures. A skillful utilization of sub-word parallelism, i.e. the parallel execution of operations on data with low word width (subwords), has a strong impact on the system performance.

In this paper we derive a method for transforming an algorithm using single instructions on sub-words to an efficient I/O equivalent algorithm using SWP-instructions on full length words (FLWs) where the sub-words have to be packed to FLWs. The method allows a full automation of this process. For architectures with parallel processing on different levels the derived algorithm on FLWs can be distributed on further higher levels of parallelism such as on several functional units and several processing elements analogous to the approach presented.

Citation:
Rainer Schaffer, Renate Merker, Francky Catthoor, "Derivation of Packing Instructions for Exploiting Sub-Word Parallelism," parelec, pp.167-172, International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06), 2006
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