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International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06)
A Delay-Optimal Static Scheduling of DSP Applications Mapped onto Multiprocessor Architectures
Bialystok, Poland
September 13-September 17
ISBN: 0-7695-2554-7
ASCII Text
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Awni Itradat, M.O. Ahmad, Ali Shatnawi, "A Delay-Optimal Static Scheduling of DSP Applications Mapped onto Multiprocessor Architectures," Parallel Computing in Electrical Engineering, International Conference on, pp. 386-391, International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06), 2006.
 
 
BibTex
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@article{ 10.1109/PARELEC.2006.2,
author = {Awni Itradat and M.O. Ahmad and Ali Shatnawi},
title = {A Delay-Optimal Static Scheduling of DSP Applications Mapped onto Multiprocessor Architectures},
journal ={Parallel Computing in Electrical Engineering, International Conference on},
volume = {0},
year = {2006},
isbn = {0-7695-2554-7},
pages = {386-391},
doi = {http://doi.ieeecomputersociety.org/10.1109/PARELEC.2006.2},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Parallel Computing in Electrical Engineering, International Conference on
TI - A Delay-Optimal Static Scheduling of DSP Applications Mapped onto Multiprocessor Architectures
SN - 0-7695-2554-7
SP386
EP391
A1 - Awni Itradat,
A1 - M.O. Ahmad,
A1 - Ali Shatnawi,
PY - 2006
KW - null
VL - 0
JA - Parallel Computing in Electrical Engineering, International Conference on
ER -
 
Awni Itradat, Concordia University, Canada
M.O. Ahmad, Concordia University, Canada
Ali Shatnawi, Jordan University of Science and Technology, Jordan
This paper presents a novel technique to obtain time schedules for cyclic DFGs representing DSP algorithms mapped onto multiprocessor systems with non-negligible inter-processor communication delays. In this paper, the question of optimizing the input/output delay in the present of inter-processor communication overhead is addressed. The proposed technique operating on the cyclic DFG of a DSP algorithm is designed to evaluate the relative firing times of the nodes by using Floyd- Warshall's longest path algorithm so that the interprocessor communication overhead is taken into consideration to provide an optimal schedule.
Citation:
Awni Itradat, M.O. Ahmad, Ali Shatnawi, "A Delay-Optimal Static Scheduling of DSP Applications Mapped onto Multiprocessor Architectures," parelec, pp.386-391, International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06), 2006
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