loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
2009 18th International Conference on Parallel Architectures and Compilation Techniques
Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading
Raleigh, North Carolina, USA
September 12-September 16
ISBN: 978-0-7695-3771-9
ASCII Text
x 
 
Leo Porter, Bumyong Choi, Dean M. Tullsen, "Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading," Parallel Architectures and Compilation Techniques, International Conference on, pp. 313-324, 2009 18th International Conference on Parallel Architectures and Compilation Techniques, 2009.
 
 
BibTex
x
 
@article{ 10.1109/PACT.2009.37,
author = {Leo Porter and Bumyong Choi and Dean M. Tullsen},
title = {Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading},
journal ={Parallel Architectures and Compilation Techniques, International Conference on},
volume = {0},
year = {2009},
issn = {1089-795X},
pages = {313-324},
doi = {http://doi.ieeecomputersociety.org/10.1109/PACT.2009.37},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Parallel Architectures and Compilation Techniques, International Conference on
TI - Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading
SN - 1089-795X
SP313
EP324
A1 - Leo Porter,
A1 - Bumyong Choi,
A1 - Dean M. Tullsen,
PY - 2009
KW - Chip Multiprocessors
KW - Speculative Multithreading
KW - Transactional Memory
VL - 0
JA - Parallel Architectures and Compilation Techniques, International Conference on
ER -
 
This research demonstrates that coming support for hardware transactional memory can be leveraged to significantly reduce the cost of implementing true speculative multithreading. In particular, it explores the path from eager conflict detection HTM to full support of efficient speculative multithreading, focusing on the case where frequent memory dependencies exist between speculative threads. The result is a unified memory architecture capable of effective support for transactional parallel workloads and efficient speculative multithreading.
Index Terms:
Chip Multiprocessors, Speculative Multithreading, Transactional Memory
Citation:
Leo Porter, Bumyong Choi, Dean M. Tullsen, "Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading," pact, pp.313-324, 2009 18th International Conference on Parallel Architectures and Compilation Techniques, 2009
Usage of this product signifies your acceptance of the Terms of Use.