16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007)
Brasov, Romania
September 15-September 19
ISBN: 0-7695-2944-5
DOI Bookmark:
http://doi.ieeecomputersociety.org/10.1109/PACT.2007.9
Technological advances along with more complex and dynamic application behavior argue for revisiting mechanisms that adapt logical cache block size to application characteristics. This approach to bridging the processor/memory performance gap has been studied in the past, but most studies used trace-driven simulation and only looked at L1 caches. Given the changes in hardware and software since these seminal studies, we revisit the general approach: we present a transparent, phase-adaptive mechanism for L2 cache block superloading with minimal hardware complexity, evaluating it on a full-system simulator running 23 SPEC CPU2000 applications run to completion using training inputs.
Citation:
Matthew A. Watkins, Sally A. McKee, Lambert Schaelicke, "A Phase-Adaptive Approach to Increasing Cache Performance," pact, pp.432, 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007), 2007
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