VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors

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16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007)

VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors (PDF)

Brasov, Romania

September 15-September 19

ISBN: 0-7695-2944-5

	ASCII Text	x
	R. Ubal, J. Sahuquillo, S. Petit, P. Lopez, J. Duato, "VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors," Parallel Architectures and Compilation Techniques, International Conference on, pp. 429, 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007), 2007.

	BibTex	x
	@article{ 10.1109/PACT.2007.78, author = {R. Ubal and J. Sahuquillo and S. Petit and P. Lopez and J. Duato}, title = {VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors}, journal ={Parallel Architectures and Compilation Techniques, International Conference on}, volume = {0}, year = {2007}, issn = {1089-795X}, pages = {429}, doi = {http://doi.ieeecomputersociety.org/10.1109/PACT.2007.78}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Parallel Architectures and Compilation Techniques, International Conference on TI - VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors SN - 1089-795X SP EP A1 - R. Ubal, A1 - J. Sahuquillo, A1 - S. Petit, A1 - P. Lopez, A1 - J. Duato, PY - 2007 KW - null VL - 0 JA - Parallel Architectures and Compilation Techniques, International Conference on ER -

R. Ubal, Universidad Politecnica de Valencia, Spain

J. Sahuquillo, Universidad Politecnica de Valencia, Spain

S. Petit, Universidad Politecnica de Valencia, Spain

P. Lopez, Universidad Politecnica de Valencia, Spain

J. Duato, Universidad Politecnica de Valencia, Spain

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PACT.2007.78

The Validation Buffer (VB) Microarchitecture [4] retires instructions out of order, by substituting the classical ROB by the VB structure. The VB removes the negative effect of long latency instructions located at the ROB head, which prevent other instructions from retiring and cause frequent pipeline stalls due to lack of space in the ROB.

Citation:

R. Ubal, J. Sahuquillo, S. Petit, P. Lopez, J. Duato, "VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors," pact, pp.429, 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007), 2007

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