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16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007)
Brasov, Romania
September 15-September 19
ISBN: 0-7695-2944-5
ASCII Text
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Sonia Lopez, Steve Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares, "Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors," Parallel Architectures and Compilation Techniques, International Conference on, pp. 416, 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007), 2007.
 
 
BibTex
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@article{ 10.1109/PACT.2007.56,
author = {Sonia Lopez and Steve Dropsho and David H. Albonesi and Oscar Garnica and Juan Lanchares},
title = {Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors},
journal ={Parallel Architectures and Compilation Techniques, International Conference on},
volume = {0},
year = {2007},
issn = {1089-795X},
pages = {416},
doi = {http://doi.ieeecomputersociety.org/10.1109/PACT.2007.56},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Parallel Architectures and Compilation Techniques, International Conference on
TI - Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors
SN - 1089-795X
SP
EP
A1 - Sonia Lopez,
A1 - Steve Dropsho,
A1 - David H. Albonesi,
A1 - Oscar Garnica,
A1 - Juan Lanchares,
PY - 2007
KW - null
VL - 0
JA - Parallel Architectures and Compilation Techniques, International Conference on
ER -
 
Sonia Lopez, Universidad Comlutense de Madrid, Spain
Steve Dropsho, EPFL, Switzerland
David H. Albonesi, Cornell University, USA
Oscar Garnica, Universidad Comlutense de Madrid, Spain
Juan Lanchares, Universidad Comlutense de Madrid, Spain
Resizable caches can tradeoff capacity for access speed to dynamically match the needs of the workload. In single-threaded cores, resizable caches adapt to the phases of the running application. In Simultaneous Multi- Threaded (SMT) cores the caching needs can vary greatly across the number of threads and their characteristics, thus, offering even more opportunities to dynamically adjust cache resources to the workload.
Citation:
Sonia Lopez, Steve Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares, "Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors," pact, pp.416, 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007), 2007
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