Power-Aware Compiler Controllable Chip Multiprocessor

	This Article
	PDF RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Hiroaki Shikano Articles by Jun Shirako Articles by Yasutaka Wada Articles by Keiji Kimura Articles by Hironori Kasahara

16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007)

Power-Aware Compiler Controllable Chip Multiprocessor (PDF)

Brasov, Romania

September 15-September 19

ISBN: 0-7695-2944-5

	ASCII Text	x
	Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Power-Aware Compiler Controllable Chip Multiprocessor," Parallel Architectures and Compilation Techniques, International Conference on, pp. 427, 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007), 2007.

	BibTex	x
	@article{ 10.1109/PACT.2007.54, author = {Hiroaki Shikano and Jun Shirako and Yasutaka Wada and Keiji Kimura and Hironori Kasahara}, title = {Power-Aware Compiler Controllable Chip Multiprocessor}, journal ={Parallel Architectures and Compilation Techniques, International Conference on}, volume = {0}, year = {2007}, issn = {1089-795X}, pages = {427}, doi = {http://doi.ieeecomputersociety.org/10.1109/PACT.2007.54}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Parallel Architectures and Compilation Techniques, International Conference on TI - Power-Aware Compiler Controllable Chip Multiprocessor SN - 1089-795X SP EP A1 - Hiroaki Shikano, A1 - Jun Shirako, A1 - Yasutaka Wada, A1 - Keiji Kimura, A1 - Hironori Kasahara, PY - 2007 KW - null VL - 0 JA - Parallel Architectures and Compilation Techniques, International Conference on ER -

Hiroaki Shikano, Waseda University, Japan; Hitachi, Ltd., Japan

Jun Shirako, Waseda University, Japan

Yasutaka Wada, Waseda University, Japan

Keiji Kimura, Waseda University, Japan

Hironori Kasahara, Waseda University, Japan

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PACT.2007.54

Chip multi-processors (CMP) have attracted much attention since they achieve higher performance not by raising operating frequency but by utilizing a number of transistors in parallel. However, simply increasing the number of processor elements (PE) will result in raising power consumption. This work presents a power-aware compiler controllable heterogeneous CMP and its performance and power evaluation with the OSCAR (Optimally SCheduled Advanced multiprocessoR) parallelizing compiler[1].

Citation:

Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Power-Aware Compiler Controllable Chip Multiprocessor," pact, pp.427, 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007), 2007

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.