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16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007)
Brasov, Romania
September 15-September 19
ISBN: 0-7695-2944-5
Hiroaki Shikano, Waseda University, Japan; Hitachi, Ltd., Japan
Jun Shirako, Waseda University, Japan
Yasutaka Wada, Waseda University, Japan
Keiji Kimura, Waseda University, Japan
Hironori Kasahara, Waseda University, Japan
Chip multi-processors (CMP) have attracted much attention since they achieve higher performance not by raising operating frequency but by utilizing a number of transistors in parallel. However, simply increasing the number of processor elements (PE) will result in raising power consumption. This work presents a power-aware compiler controllable heterogeneous CMP and its performance and power evaluation with the OSCAR (Optimally SCheduled Advanced multiprocessoR) parallelizing compiler[1].
Citation:
Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Power-Aware Compiler Controllable Chip Multiprocessor," pact, pp.427, 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007), 2007
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