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16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007)
Brasov, Romania
September 15-September 19
ISBN: 0-7695-2944-5
ASCII Text
x 
 
Kaushik Rajan , R. Govindarajan, Bharadwaj Amrutur, "Dynamic Cache Placement with Two-level Mapping to Reduce Conflict Misses," Parallel Architectures and Compilation Techniques, International Conference on, pp. 422, 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007), 2007.
 
 
BibTex
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@article{ 10.1109/PACT.2007.27,
author = {Kaushik Rajan and R. Govindarajan and Bharadwaj Amrutur},
title = {Dynamic Cache Placement with Two-level Mapping to Reduce Conflict Misses},
journal ={Parallel Architectures and Compilation Techniques, International Conference on},
volume = {0},
year = {2007},
issn = {1089-795X},
pages = {422},
doi = {http://doi.ieeecomputersociety.org/10.1109/PACT.2007.27},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Parallel Architectures and Compilation Techniques, International Conference on
TI - Dynamic Cache Placement with Two-level Mapping to Reduce Conflict Misses
SN - 1089-795X
SP
EP
A1 - Kaushik Rajan ,
A1 - R. Govindarajan,
A1 - Bharadwaj Amrutur,
PY - 2007
KW - null
VL - 0
JA - Parallel Architectures and Compilation Techniques, International Conference on
ER -
 
Kaushik Rajan, Indian Institute of Science, India
R. Govindarajan, Indian Institute of Science, India
Bharadwaj Amrutur, Indian Institute of Science, India
Due to the tight coupling between processor cycle time and L1 access time, L1 caches are typically small and have low associativities. As a consequence they incur a higher percentage of conflict misses than lower level caches. The extent of conflict depends on the memory access pattern exhibited by the program, and can vary from program to program. By using a fixed set of bits to index the cache, conventional mapping enforces the same rigid mapping from address to cache set for all programs. This results in a nonuniform distribution of addresses among cache sets causing unnecessary conflict misses. Such conflicts could be avoided if some flexibility in mapping is exercised.
Citation:
Kaushik Rajan , R. Govindarajan, Bharadwaj Amrutur, "Dynamic Cache Placement with Two-level Mapping to Reduce Conflict Misses," pact, pp.422, 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007), 2007
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