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16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007)
Brasov, Romania
September 15-September 19
ISBN: 0-7695-2944-5
Jing Yu, University of Illinois at Urbana-Champaign, USA
Maria Jesus Garzaran, University of Illinois at Urbana-Champaign, USA
Dramatic increases in the number of transistors that can be integrated on a chip will make the hardware more susceptible to radiation-induced transient errors. Highend architectures like the IBM mainframes, HP NonStop or mission-critical computers are likely to include several hardware-intensive fault tolerance techniques. However, the commodity chips which are cost- and energy-constrained, will need a more flexible and inexpensive technology for error detection. Software approaches can play a major role for this sector of the market because they need little hardware modification and can be tailored to fit different requirements of reliability and performance.
Citation:
Jing Yu, Maria Jesus Garzaran, "Compiler Optimizations for Fault Tolerance Software Checking," pact, pp.433, 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007), 2007
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