Analyzing SEU Effects in SRAM-based FPGAs

I
IOLTS
2003
9th IEEE International On-Line Testing Symposium
Abstract - Analyzing SEU Effects in SRAM-based FPGAs

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9th IEEE International On-Line Testing Symposium

Kos Island, Greece

July 07-July 09

ISBN: 0-7695-1968-7

	ASCII Text	x
	M. Violante, M. Ceschia, M. Sonza Reorda, A. Paccagnella, P. Bernardi, M. Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori, "Analyzing SEU Effects in SRAM-based FPGAs," On-Line Testing Symposium, IEEE International, pp. 119, 9th IEEE International On-Line Testing Symposium, 2003.

	BibTex	x
	@article{ 10.1109/OLT.2003.1214377, author = {M. Violante and M. Ceschia and M. Sonza Reorda and A. Paccagnella and P. Bernardi and M. Rebaudengo and D. Bortolato and M. Bellato and P. Zambolin and A. Candelori}, title = {Analyzing SEU Effects in SRAM-based FPGAs}, journal ={On-Line Testing Symposium, IEEE International}, volume = {0}, year = {2003}, isbn = {0-7695-1968-7}, pages = {119}, doi = {http://doi.ieeecomputersociety.org/10.1109/OLT.2003.1214377}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - On-Line Testing Symposium, IEEE International TI - Analyzing SEU Effects in SRAM-based FPGAs SN - 0-7695-1968-7 SP EP A1 - M. Violante, A1 - M. Ceschia, A1 - M. Sonza Reorda, A1 - A. Paccagnella, A1 - P. Bernardi, A1 - M. Rebaudengo, A1 - D. Bortolato, A1 - M. Bellato, A1 - P. Zambolin, A1 - A. Candelori, PY - 2003 KW - null VL - 0 JA - On-Line Testing Symposium, IEEE International ER -

M. Violante, Politecnico di Torino

M. Ceschia, Universit? di Padova; Istituto Nazionale di Fisica Nucleare

M. Sonza Reorda, Politecnico di Torino

A. Paccagnella, Universit? di Padova; Istituto Nazionale di Fisica Nucleare

P. Bernardi, Politecnico di Torino

M. Rebaudengo, Politecnico di Torino

D. Bortolato, Universit? di Padova

M. Bellato, Istituto Nazionale di Fisica Nucleare

P. Zambolin, Universit? di Padova

A. Candelori, Istituto Nazionale di Fisica Nucleare

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/OLT.2003.1214377

Commercial-Off-The-Shelf SRAM-based FPGA devices are becoming of interests for applications where high dependability and low cost are mandatory constraints. This paper proposes a new method for assessing the effects of SEUs in the device configuration memory. The method combines radiation testing for technology characterization and simulation-based fault injection for SEU propagation. Experimental results we gathered with the purpose of modeling the effects of SEUs in the FPGA configuration memory are reported and commented.

Citation:

M. Violante, M. Ceschia, M. Sonza Reorda, A. Paccagnella, P. Bernardi, M. Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori, "Analyzing SEU Effects in SRAM-based FPGAs," iolts, pp.119, 9th IEEE International On-Line Testing Symposium, 2003

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