Seventh International On-Line Testing Workshop A Gated Clock Scheme for Low Power Scan-Based BIST Taormina, Italy July 09-July 11 ISBN: 0-7695-1290-9
Abstract: In this paper, we present a new low power scan-based BIST technique which can reduce the switching activity during test operation. The proposed low power/energy technique is based on a gated clock scheme for the scan path and the clock tree feeding the scan path.
Citation:
Y. Bonhomme P. Girard L. Guiller C. Landrault, S. Pravossoudovitch, "A Gated Clock Scheme for Low Power Scan-Based BIST," ioltw, pp.0087, Seventh International On-Line Testing Workshop, 2001 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||