Novel Fault-Tolerant Adder Design for FPGA-Based Systems

I
IOLTW
2001
Seventh International On-Line Testing Workshop
Abstract - Novel Fault-Tolerant Adder Design for FPGA-Based Systems

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	Similar Articles Articles by Monica Alderighi Articles by Sergio D'Angelo Articles by Giacomo R. Sechi Articles by Cecilia Metra

Seventh International On-Line Testing Workshop

Taormina, Italy

July 09-July 11

ISBN: 0-7695-1290-9

	ASCII Text	x
	Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi, Cecilia Metra, "Novel Fault-Tolerant Adder Design for FPGA-Based Systems," On-Line Testing Workshop, IEEE International, pp. 0054, Seventh International On-Line Testing Workshop, 2001.

	BibTex	x
	@article{ 10.1109/OLT.2001.937819, author = {Monica Alderighi and Sergio D'Angelo and Giacomo R. Sechi and Cecilia Metra}, title = {Novel Fault-Tolerant Adder Design for FPGA-Based Systems}, journal ={On-Line Testing Workshop, IEEE International}, volume = {0}, year = {2001}, isbn = {0-7695-1290-9}, pages = {0054}, doi = {http://doi.ieeecomputersociety.org/10.1109/OLT.2001.937819}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - On-Line Testing Workshop, IEEE International TI - Novel Fault-Tolerant Adder Design for FPGA-Based Systems SN - 0-7695-1290-9 SP EP A1 - Monica Alderighi, A1 - Sergio D'Angelo, A1 - Giacomo R. Sechi, A1 - Cecilia Metra, PY - 2001 VL - 0 JA - On-Line Testing Workshop, IEEE International ER -

Monica Alderighi, Consiglio Nazionale delle Ricerche

Sergio D'Angelo, Consiglio Nazionale delle Ricerche

Giacomo R. Sechi, Consiglio Nazionale delle Ricerche

Cecilia Metra, Universita' di Bologna

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/OLT.2001.937819

Abstract: In this paper we propose a novel fault-tolerant adder which is suitable to be used for highly dependable systems implemented by means of Field-Programmable Gate Arrays (FPGAs). Compared to alternate conventional designs, the one presented here allows to achieve fault-tolerance at lower design costs. A prototype has been developed, whose expected behavior has been verified by means of post-layout simulations and experimental measurements. Although our adder has been conceived for FPGA-based systems, it is also suitable to be implemented by means of VLSI and very deep sub-micron technologies.

Citation:

Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi, Cecilia Metra, "Novel Fault-Tolerant Adder Design for FPGA-Based Systems," ioltw, pp.0054, Seventh International On-Line Testing Workshop, 2001

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