Testing FPGA Delay Faults in the System Environment is Very Different from "Ordinary" Delay Fault Testing

I
IOLTW
2001
Seventh International On-Line Testing Workshop
Abstract - Testing FPGA Delay Faults in the System Environment is Very Different from "Ordinary" Delay Fault Testing

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	Similar Articles Articles by Andrzej Krasniewski

Seventh International On-Line Testing Workshop

Taormina, Italy

July 09-July 11

ISBN: 0-7695-1290-9

	ASCII Text	x
	Andrzej Krasniewski, "Testing FPGA Delay Faults in the System Environment is Very Different from "Ordinary" Delay Fault Testing," On-Line Testing Workshop, IEEE International, pp. 0037, Seventh International On-Line Testing Workshop, 2001.

	BibTex	x
	@article{ 10.1109/OLT.2001.937815, author = {Andrzej Krasniewski}, title = {Testing FPGA Delay Faults in the System Environment is Very Different from "Ordinary" Delay Fault Testing}, journal ={On-Line Testing Workshop, IEEE International}, volume = {0}, year = {2001}, isbn = {0-7695-1290-9}, pages = {0037}, doi = {http://doi.ieeecomputersociety.org/10.1109/OLT.2001.937815}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - On-Line Testing Workshop, IEEE International TI - Testing FPGA Delay Faults in the System Environment is Very Different from "Ordinary" Delay Fault Testing SN - 0-7695-1290-9 SP EP A1 - Andrzej Krasniewski, PY - 2001 VL - 0 JA - On-Line Testing Workshop, IEEE International ER -

Andrzej Krasniewski, Warsaw University of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/OLT.2001.937815

Abstract: We explain differences between testing delay faults in FPGAs and testing delay faults in circuits whose combinational sections can be represented as gate networks. We formulate - in a form suitable for analysis of LUT-based FPGAs - conditions that allow one to check whether or not a given input pair is a test of specific type (non-robust, robust, etc.). The presented theoretical results are shown to simplify an analysis of the various methods for enhancing the effectiveness of detection of FPGA delay faults.

Citation:

Andrzej Krasniewski, "Testing FPGA Delay Faults in the System Environment is Very Different from "Ordinary" Delay Fault Testing," ioltw, pp.0037, Seventh International On-Line Testing Workshop, 2001

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