Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008)
A Lightweight Fault-Tolerant Mechanism for Network-on-Chip
April 07-April 10
ISBN: 978-0-7695-3098-7
Survival capability is becoming a crucial factor in designing multicore processors built with on-chip packet networks, or networks on chip (NoCs).??In this paper, we propose a lightweight fault-tolerant mechanism for NoCs based on default backup paths (DBPs) designed to maintain, in the presence of failures, network connectivity of both non-faulty routers as well as healthy processor cores which may be connected to faulty routers. The mechanism provides default paths as backup between certain router ports which serve as alternative datapaths to circumvent failed components within a faulty router. Along with a minimal subset of normal network channels, the set of default backup paths internal to faulty routers form---in the worst case---a unidirectional ring topology that provides network-wide connectivity to all processor cores.??Routing using the DBP mechanism is proved to be deadlock-free with only two virtual channels even for fault scenarios in which regular networks degrade to irregular (arbitrary) topologies. Evaluation results show that, for a 2-D mesh wormhole NoC, only 12.6% additional hardware resources are needed to implement the proposed DBP mechanism in order to provide graceful performance degradation without chip-wide failure as the number of faults increases to the maximum needed to form ring.
Index Terms:
Network-on-Chip, on-chip network, reliability, fault tolerance, routing algorithm, deadlock avoidance
Citation:
Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy Mark Pinkston, "A Lightweight Fault-Tolerant Mechanism for Network-on-Chip," nocs, pp.13-22, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 2008