Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008) Implementation of Wave-Pipelined Interconnects in FPGAs April 07-April 10 ISBN: 978-0-7695-3098-7
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/NOCS.2008.32
Global interconnection and communication at high clock frequencies are becoming more problematic in FPGA. In this paper, we address this problem by presenting an interconnect wave-pipelining strategy, which utilizes the existing programmable interconnects fabrics to provide high-throughput communication in FPGA. Two design approaches for interconnect wave-pipelining, using simple clock phase shifting and asynchronous phase encoding, are presented in this paper. Experimental results from a Xilinx Virtex-5 FPGA device are also presented.
Citation:
Terrence Mak, Crescenzo D'Alessandro, Pete Sedcole, Peter Y.K. Cheung, Alex Yakovlev, Wayne Luk, "Implementation of Wave-Pipelined Interconnects in FPGAs," nocs, pp.213-214, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 2008 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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