Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms

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	Similar Articles Articles by Maurizio Palesi Articles by Giuseppe Longo Articles by Salvatore Signorino Articles by Rickard Holsmark Articles by Shashi Kumar Articles by Vincenzo Catania

Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008)

April 07-April 10

ISBN: 978-0-7695-3098-7

	ASCII Text	x
	Maurizio Palesi, Giuseppe Longo, Salvatore Signorino, Rickard Holsmark, Shashi Kumar, Vincenzo Catania, "Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms," Networks-on-Chip, International Symposium on, pp. 97-106, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 2008.

	BibTex	x
	@article{ 10.1109/NOCS.2008.31, author = {Maurizio Palesi and Giuseppe Longo and Salvatore Signorino and Rickard Holsmark and Shashi Kumar and Vincenzo Catania}, title = {Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms}, journal ={Networks-on-Chip, International Symposium on}, volume = {0}, year = {2008}, isbn = {978-0-7695-3098-7}, pages = {97-106}, doi = {http://doi.ieeecomputersociety.org/10.1109/NOCS.2008.31}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Networks-on-Chip, International Symposium on TI - Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms SN - 978-0-7695-3098-7 SP97 EP106 A1 - Maurizio Palesi, A1 - Giuseppe Longo, A1 - Salvatore Signorino, A1 - Rickard Holsmark, A1 - Shashi Kumar, A1 - Vincenzo Catania, PY - 2008 KW - Network on Chip KW - Routing Algorithm KW - Router Design KW - Deadlock KW - Application Specific Routing KW - Congestion. VL - 0 JA - Networks-on-Chip, International Symposium on ER -

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/NOCS.2008.31

In this paper we demonstrate that it is possible to design highly efficient application specific routing algorithms which distribute traffic more uniformly by using information regarding applications communication behavior (communication topology and communication bandwidth). We use off-line analysis to estimate expected load on various links in the network. The result of this analysis is used along with the available routing adaptivity in each router to distribute less traffic to links and paths which are expected to be congested. The methodology for Application Specific Routing Algorithms (APSRA) is extended to incorporate these features to design highly adaptive deadlock free routing algorithms which also distribute traffic more uniformly and reduce network congestion. We show that the number of congested links (links exceeding threshold bandwidth) is reduced by up to 100% with this extension. Significant reduction in average delay is also obtained for both synthetic (up to 25%) as well as a real application (12.5%) communication traffic with this extension to APSRA. We discuss architectural implications and area overhead of our approach on the design of a table based NoC router.

Index Terms:

Network on Chip, Routing Algorithm, Router Design, Deadlock, Application Specific Routing, Congestion.

Citation:

Maurizio Palesi, Giuseppe Longo, Salvatore Signorino, Rickard Holsmark, Shashi Kumar, Vincenzo Catania, "Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms," nocs, pp.97-106, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 2008

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