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Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008)
Simulation and Evaluation of On-Chip Interconnect Architectures: 2D Mesh, Spidergon, and WK-Recursive Network
April 07-April 10
ISBN: 978-0-7695-3098-7
ASCII Text
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S. Suboh, M. Bakhouya, T. El-Ghazawi, "Simulation and Evaluation of On-Chip Interconnect Architectures: 2D Mesh, Spidergon, and WK-Recursive Network," Networks-on-Chip, International Symposium on, pp. 205-206, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 2008.
 
 
BibTex
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@article{ 10.1109/NOCS.2008.25,
author = {S. Suboh and M. Bakhouya and T. El-Ghazawi},
title = {Simulation and Evaluation of On-Chip Interconnect Architectures: 2D Mesh, Spidergon, and WK-Recursive Network},
journal ={Networks-on-Chip, International Symposium on},
volume = {0},
year = {2008},
isbn = {978-0-7695-3098-7},
pages = {205-206},
doi = {http://doi.ieeecomputersociety.org/10.1109/NOCS.2008.25},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Networks-on-Chip, International Symposium on
TI - Simulation and Evaluation of On-Chip Interconnect Architectures: 2D Mesh, Spidergon, and WK-Recursive Network
SN - 978-0-7695-3098-7
SP205
EP206
A1 - S. Suboh,
A1 - M. Bakhouya,
A1 - T. El-Ghazawi,
PY - 2008
KW - System on Chip
KW - Network on Chip
KW - Modeling and simulation
KW - On Chip Interconnects
VL - 0
JA - Networks-on-Chip, International Symposium on
ER -
 
Network-on-chip has been proposed as an alternative to bus-based system to achieve high performance and scalability. The topology of on-chip interconnect plays a crucial role in System on chip performance, energy, and area requirements. In this paper, an on-chip interconnects architecture based on WK-recursive network is proposed. WK-recursive structure is analyzed and compared to 2D mesh and Spidergon structures. Simulation results show that WK-Recursive on-chip interconnect generally outperforms the other architectures.
Index Terms:
System on Chip, Network on Chip, Modeling and simulation, On Chip Interconnects
Citation:
S. Suboh, M. Bakhouya, T. El-Ghazawi, "Simulation and Evaluation of On-Chip Interconnect Architectures: 2D Mesh, Spidergon, and WK-Recursive Network," nocs, pp.205-206, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 2008
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