Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008)
A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application
April 07-April 10
ISBN: 978-0-7695-3098-7
Asynchronous design offers an attractive solution to overcome the problems faced by Networks-on-Chip (NoC) designers such as timing constraints. Nevertheless, post-fabrication testing is a big challenge to bring the asynchronous NoCs to the market due to a lack of testing methodology and support. This paper first presents the design and implementation of a Design-for-Test (DfT) architecture, which improves the testability of an asynchronous NoC architec-ture. Then, a simple method for generating test patterns for network routers is described. Test patterns are automatically generated by a custom program, given the network topology and the network size. Finally, we introduce a testing strategy for the whole asynchronous NoC. With the generated test patterns, the testing methodology presents high fault coverage (99.86%) for single stuck-at fault models.
Index Terms:
Network-on-Chip, NoC, Design-for-Test, DfT, NoC testing, SoC testing, testing methodology, testability, on-chip communication, Globally Asynchronous - Locally Synchronous, GALS, QDI asynchronous logic
Citation:
Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach, "A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application," nocs, pp.149-158, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 2008
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