Our investigation into Networks-on-Chip for Field-Programmable Gate Arrays (FPGAs) indicates that fine-grain time-division multiplexing over configurable wires can significantly reduce the number of interconnects needed and therefore reduce chip area. We have investigated the impact of using different proportions of time-multiplexed shared wiring and conventional wiring on the number of wires needed per channel. To do this we have written a scheduler to map benchmarks to the wire sharing architecture. The algorithm developed allows us to trade off between wire count and latency. This is the first time that the statically configured FPGA wiring has been entirely replaced by time-multiplexed wiring. Our results indicate that time-multiplexed wiring could be an effective way of making better use of the on-chip resources and enable the use of on-chip networks with low overheads.