Networks on Chips provide structured solutions for fast and low-power interconnect, but need to be adapted to the performance and physical design requirements of the host chip. Efficient and optimal design of such networks is an error-prone, tedious and time-consuming task. Thus, NoCs require design environments in which the network can be instantiated and tuned automatically, and where the designer steers the design by providing high level models of requirements and constraints. This talk will survey the state of the art in design automation for NoCs.