Simulation Experiments of a High-Performance RapidIO-based Processing Architecture

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by J. Adams Articles by C. Katsinis Articles by W. Rosen Articles by D. Hecht Articles by V. Adams Articles by H.V. Narravula Articles by S. Sukhtankar

IEEE International Symposium on Network Computing and Applications (NCA'01)

Cambridge, Massachusette

October 08-October 10

ISBN: 0-7695-1432-4

	ASCII Text	x
	J. Adams, C. Katsinis, W. Rosen, D. Hecht, V. Adams, H.V. Narravula, S. Sukhtankar, "Simulation Experiments of a High-Performance RapidIO-based Processing Architecture," Network Computing and Applications, IEEE International Symposium on, pp. 0336, IEEE International Symposium on Network Computing and Applications (NCA'01), 2001.

	BibTex	x
	@article{ 10.1109/NCA.2001.962550, author = {J. Adams and C. Katsinis and W. Rosen and D. Hecht and V. Adams and H.V. Narravula and S. Sukhtankar}, title = {Simulation Experiments of a High-Performance RapidIO-based Processing Architecture}, journal ={Network Computing and Applications, IEEE International Symposium on}, volume = {0}, year = {2001}, isbn = {0-7695-1432-4}, pages = {0336}, doi = {http://doi.ieeecomputersociety.org/10.1109/NCA.2001.962550}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Network Computing and Applications, IEEE International Symposium on TI - Simulation Experiments of a High-Performance RapidIO-based Processing Architecture SN - 0-7695-1432-4 SP EP A1 - J. Adams, A1 - C. Katsinis, A1 - W. Rosen, A1 - D. Hecht, A1 - V. Adams, A1 - H.V. Narravula, A1 - S. Sukhtankar, PY - 2001 KW - RapidIO KW - High Performance Commodity Network KW - Processor Interconnect KW - RapidIO Simulation VL - 0 JA - Network Computing and Applications, IEEE International Symposium on ER -

J. Adams, Rydal Research and Development, Inc.,

C. Katsinis, Drexel University

W. Rosen, Drexel University

D. Hecht, Drexel University

V. Adams, Drexel University

H.V. Narravula, Drexel University

S. Sukhtankar, Drexel University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/NCA.2001.962550

R.LachenmaierNaval Air Warfare CenterIn this paper we describe the results of our simulation analysis of a high-performance processing architecture based on the RapidIO network protocol. RapidIO is a 10 Gb/s, low-latency packet-switched interconnect technology designed for processor-to-processor, processor-to-memory, and processor-to-peripheral interconnects. Two network topologies were simulated, a simple network consisting of an 8-port switch and 8 processing nodes and a more extensive network consisting of five 8-port switches and 24 processing nodes. Results indicate that latencies as low as 92 ns for a remote 64-bit read request/response transaction may be achieved in an unloaded single-switch system. The effectiveness of various flow control mechanisms provided by the protocol are also explored, and when used in combination a 10% increase in link utilization is achieved.

Index Terms:

RapidIO, High Performance Commodity Network, Processor Interconnect, RapidIO Simulation

Citation:

J. Adams, C. Katsinis, W. Rosen, D. Hecht, V. Adams, H.V. Narravula, S. Sukhtankar, "Simulation Experiments of a High-Performance RapidIO-based Processing Architecture," nca, pp.0336, IEEE International Symposium on Network Computing and Applications (NCA'01), 2001

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.