Many researchers have been interested in the processor-memory bottleneck problem. Quite a few image applications are only interested in one or more partial regions in the images. This paper proposes an efficient multi-access memory scheme for these image applications with multiple interested regions. A multi-module memory structure is presented between the main memory and the processingunits, which achieves conflict-free parallel access of randomly aligned rectangular blocks of data in the interested regions. To increase the accessing efficiency, only interested regions are transmitted from main memory to secondary multi-module memory structure, and overlapped data between different regions are reused without retransfer. The addressing scheme of secondary multi-modulememory is not based on predetermined addressing function, but based on a table structure mapping virtual addresses of required data to physical addresses of secondary memory modules, which increases data reusability without losing addressing consistency. The table content is updated for addressing consistency every time processing a new region. The proposed twin-table structure and block-reschedulingscheme reduce the addressing latency. Synthesis results on FPGA indicate small hardware costs for a range of access pattern dimensions. Significant transfer speedups in our experiments are achieved when compared with the scheme that accesses main memory directly.