Identifying the root-cause of silicon failures is crucial for silicon debug and yield improvement. However, due to the low visibility of silicon data, root-cause identification tends to be a painful process. In this paper, we develop a systematic framework to diagnose silicon failures under functional test patterns. We propose a novel scan-dump approach to isolate critical cycles. Within the critical cycles, we apply logic-reasoning techniques including active-path-tracing (AP) and what-if (WI) analysis to automatically extract and rank failure candidates. We apply our framework on an industrial circuit and demonstrate the promising results.