Detailed pre-silicon analysis and validation of new features incorporated in high performance microprocessors often requires the use of RTL and gate-level models because accurate higher-level models of such features are not available. While the results of such studies can be very valuable, this approach is both slow and complex, resulting in extreme constraints on the maximum size of workloads that can be studied. Although micro-benchmarks can be used for this purpose, it is also desirable to characterize important new features using real-world workloads. Thus, a flow for characterizing new features using detailed RTL models requires workload sampling techniques. Existing workload sampling techniques use predefined metrics to identify representative samples of the workload, but these metrics may not encompass the requirements of a given study. A more flexible approach towards specifying arbitrary metrics is needed to enable extraction of representative samples of workloads that exercise specific features of the microprocessor. In this paper, we present Workload Slicing Flow as a set of tools that enables the selection of representative workload slices satisfying a set of metrics and constraints. The use of the flow is illustrated by selecting slices for power-characterization of the floating-point unit of a research microprocessor. The selected slices represent 4% of the original workload size, and result in power estimates within 2% of the full workload power estimates.