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Sixth International Workshop on Microprocessor Test and Verification (MTV'05)
Search-Space Optimizations for High-Level ATPG
Austin, Texas
November 03-November 05
ISBN: 0-7695-2627-6
ASCII Text
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Jorge Campos, Hussain Al-Asaad, "Search-Space Optimizations for High-Level ATPG," Microprocessor Test and Verification, International Workshop on, pp. 84-89, Sixth International Workshop on Microprocessor Test and Verification (MTV'05), 2005.
 
 
BibTex
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@article{ 10.1109/MTV.2005.23,
author = {Jorge Campos and Hussain Al-Asaad},
title = {Search-Space Optimizations for High-Level ATPG},
journal ={Microprocessor Test and Verification, International Workshop on},
volume = {0},
year = {2005},
issn = {1550-4093},
pages = {84-89},
doi = {http://doi.ieeecomputersociety.org/10.1109/MTV.2005.23},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Microprocessor Test and Verification, International Workshop on
TI - Search-Space Optimizations for High-Level ATPG
SN - 1550-4093
SP84
EP89
A1 - Jorge Campos,
A1 - Hussain Al-Asaad,
PY - 2005
KW - null
VL - 0
JA - Microprocessor Test and Verification, International Workshop on
ER -
 
Jorge Campos, University of California, Davis, USA
Hussain Al-Asaad, University of California, Davis, USA
Our mutation based validation paradigm (MVP) is a validation environment for high-level microprocessor implementations. To be able to efficiently identify and analyze the architectural states (prospect states) that can possibly satisfy a set of constraints during MVP?s test generation, we need to reduce the search space in the analysis process as early as possible. In this paper, we present some optimizations in the search space that speed up the overall test generation process.
Citation:
Jorge Campos, Hussain Al-Asaad, "Search-Space Optimizations for High-Level ATPG," mtv, pp.84-89, Sixth International Workshop on Microprocessor Test and Verification (MTV'05), 2005
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