Due to increasing demand for faster computations, deeply pipelined processor architectures are being employed to meet desired system performance. Functional validation of such pipelined processors is one of the most complex and expensive tasks in the current Systems-on- Chip design methodology. While language-based validation techniques have proposed several promising ideas, many challenges remain in applying them to realistic pipelined processors. This paper describes two practical challenges in this methodology: test generation and equivalence checking. The time and resources required for test generation using the existing approaches can be extremely large for today?s pipelined processors. Similarly, traditional equivalence checkers are not useful in the context of language-driven model generation and functional validation. This paper outlines our plan to address these challenges using satisfiability checking.