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Fourth International Workshop on Microprocessor Test and Verification Common Challenges and Solutions
DeepTrans - A Model-based Approach to Functional Verification of Address Translation Mechanisms
Hyatt Town Lake Hotel, Austin, Texas
May 29-May 30
ISBN: 0-7695-2045-6
ASCII Text
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Allon Adir, Roy Emek, Yoav Katz, Anatoly Koyfman, "DeepTrans - A Model-based Approach to Functional Verification of Address Translation Mechanisms," Microprocessor Test and Verification, International Workshop on, pp. 3, Fourth International Workshop on Microprocessor Test and Verification Common Challenges and Solutions, 2003.
 
 
BibTex
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@article{ 10.1109/MTV.2003.1250255,
author = {Allon Adir and Roy Emek and Yoav Katz and Anatoly Koyfman},
title = {DeepTrans - A Model-based Approach to Functional Verification of Address Translation Mechanisms},
journal ={Microprocessor Test and Verification, International Workshop on},
volume = {0},
year = {2003},
isbn = {0-7695-2045-6},
pages = {3},
doi = {http://doi.ieeecomputersociety.org/10.1109/MTV.2003.1250255},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Microprocessor Test and Verification, International Workshop on
TI - DeepTrans - A Model-based Approach to Functional Verification of Address Translation Mechanisms
SN - 0-7695-2045-6
SP
EP
A1 - Allon Adir,
A1 - Roy Emek,
A1 - Yoav Katz,
A1 - Anatoly Koyfman,
PY - 2003
KW - null
VL - 0
JA - Microprocessor Test and Verification, International Workshop on
ER -
 
Allon Adir, IBM Research Laboratory in Haifa
Roy Emek, IBM Research Laboratory in Haifa
Yoav Katz, IBM Research Laboratory in Haifa
Anatoly Koyfman, IBM Research Laboratory in Haifa
This paper presents a new test case generation technology, specifically targeted at verifying systems that include address translation mechanisms. The ever-growing demand for performance makes these mechanisms more complex, thereby increasing the risk of bugs and increasing the need for such technology. DeepTrans is a package that provides model-based test generation capabilities to verify translation mechanisms based on a modeling language. The modeling language includes constructs for describing the address translation process, commonly used translation resources, and architecture rules related to translation. Deep-Trans is currently used by two different IBM test generators.
Citation:
Allon Adir, Roy Emek, Yoav Katz, Anatoly Koyfman, "DeepTrans - A Model-based Approach to Functional Verification of Address Translation Mechanisms," mtv, pp.3, Fourth International Workshop on Microprocessor Test and Verification Common Challenges and Solutions, 2003
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