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2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06)
Taipei, Taiwan
August 02-August 04
ISBN: 0-7695-2572-5
ASCII Text
x 
 
Riichiro Shirota, "Roadmap of the Flash Memory," Memory Technology, Design and Testin, IEEE International Workshop on, pp. xiii, 2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06), 2006.
 
 
BibTex
x
 
@article{ 10.1109/MTDT.2006.27,
author = {Riichiro Shirota},
title = {Roadmap of the Flash Memory},
journal ={Memory Technology, Design and Testin, IEEE International Workshop on},
volume = {0},
year = {2006},
issn = {1087-4852},
pages = {xiii},
doi = {http://doi.ieeecomputersociety.org/10.1109/MTDT.2006.27},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Memory Technology, Design and Testin, IEEE International Workshop on
TI - Roadmap of the Flash Memory
SN - 1087-4852
SP
EP
A1 - Riichiro Shirota,
PY - 2006
KW - null
VL - 0
JA - Memory Technology, Design and Testin, IEEE International Workshop on
ER -
 
Riichiro Shirota, Toshiba, Japan
It has become 19 years, since the development of the NAND Flash started using 0.7..m rule in 1987. The speed of the scaling has been very fast and the period of the product of the new generation is less than 2 years. Now, design rule of the NAND Flash memory has become less than 70nm. There are some problems to interfere with the scaling of the memory cell. Basic idea to overcome these problems will be introduced in this talk.
Citation:
Riichiro Shirota, "Roadmap of the Flash Memory," mtdt, pp.xiii, 2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06), 2006
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