An Integrated Memory Self Test and EDA Solution

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Records of the 2004 International Workshop on Memory Technology, Design and Testing (MTDT'04)

San Jose, California, USA

August 09-August 10

ISBN: 0-7695-2193-2

	ASCII Text	x
	R. Dean Adams, Robert Abbott, Xiaoliang Bai, Dwayne Burek, Eric MacDonald, "An Integrated Memory Self Test and EDA Solution," Memory Technology, Design and Testin, IEEE International Workshop on, pp. 92-95, Records of the 2004 International Workshop on Memory Technology, Design and Testing (MTDT'04), 2004.

	BibTex	x
	@article{ 10.1109/MTDT.2004.5, author = {R. Dean Adams and Robert Abbott and Xiaoliang Bai and Dwayne Burek and Eric MacDonald}, title = {An Integrated Memory Self Test and EDA Solution}, journal ={Memory Technology, Design and Testin, IEEE International Workshop on}, volume = {0}, year = {2004}, issn = {1087-4852}, pages = {92-95}, doi = {http://doi.ieeecomputersociety.org/10.1109/MTDT.2004.5}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Memory Technology, Design and Testin, IEEE International Workshop on TI - An Integrated Memory Self Test and EDA Solution SN - 1087-4852 SP92 EP95 A1 - R. Dean Adams, A1 - Robert Abbott, A1 - Xiaoliang Bai, A1 - Dwayne Burek, A1 - Eric MacDonald, PY - 2004 VL - 0 JA - Memory Technology, Design and Testin, IEEE International Workshop on ER -

R. Dean Adams, Magma Design Automation

Robert Abbott, Magma Design Automation

Xiaoliang Bai, Magma Design Automation

Dwayne Burek, Magma Design Automation

Eric MacDonald, University of Texas at El Paso

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MTDT.2004.5

Memory built-in self-test (BIST) is a critical portion of the chip design and electronic design automation (EDA) flow. A BIST tool needs to understand the memory at the topological and layout levels in order to test for the correct fault models. The BIST also needs to be fully integrated into the overall EDA flow in order to have the least impact on chip area and have the greatest ease of use to the chip designer.

Citation:

R. Dean Adams, Robert Abbott, Xiaoliang Bai, Dwayne Burek, Eric MacDonald, "An Integrated Memory Self Test and EDA Solution," mtdt, pp.92-95, Records of the 2004 International Workshop on Memory Technology, Design and Testing (MTDT'04), 2004

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