Hundreds of memory cores can be found on a typical system-on-chip (SOC) today. Diagnosing such a large number of memory cores using a conventional built-in self-test (BIST) architecture consumes too much time, as its on-chip diagnostics support is for sequential diagnosis only. In this paper, we present a memory BIST architecture with parallel diagnosis scheme. The proposed parallel built-in self-diagnosis (PBISD) scheme was developed to work with our existing Memory Optimization and REconfiguration (MORE) system, which configures small memory cores into the large one specified by the user, subject to the power and geometry constraints. With PBISD and MORE, memory test and diagnosis can be done in a much shorter time, and the whole system provides a good balance among test time, test power, and test hardware overhead. Experimental results show that, when compared with a conventional BISD scheme, the diagnosis time for a case with four memory cores is only 25%. Moreover, the area overhead is only 49%, as only one test pattern generator is required.