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Records of the 2004 International Workshop on Memory Technology, Design and Testing (MTDT'04)
The State-of-Art and Future Trends in Testing Embedded Memories
San Jose, California, USA
August 09-August 10
ISBN: 0-7695-2193-2
ASCII Text
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Said Hamdioui, Georgi Gaydadjiev, Ad J. van de Goor, "The State-of-Art and Future Trends in Testing Embedded Memories," Memory Technology, Design and Testin, IEEE International Workshop on, pp. 54-59, Records of the 2004 International Workshop on Memory Technology, Design and Testing (MTDT'04), 2004.
 
 
BibTex
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@article{ 10.1109/MTDT.2004.23,
author = {Said Hamdioui and Georgi Gaydadjiev and Ad J. van de Goor},
title = {The State-of-Art and Future Trends in Testing Embedded Memories},
journal ={Memory Technology, Design and Testin, IEEE International Workshop on},
volume = {0},
year = {2004},
issn = {1087-4852},
pages = {54-59},
doi = {http://doi.ieeecomputersociety.org/10.1109/MTDT.2004.23},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Memory Technology, Design and Testin, IEEE International Workshop on
TI - The State-of-Art and Future Trends in Testing Embedded Memories
SN - 1087-4852
SP54
EP59
A1 - Said Hamdioui,
A1 - Georgi Gaydadjiev,
A1 - Ad J. van de Goor,
PY - 2004
KW - null
VL - 0
JA - Memory Technology, Design and Testin, IEEE International Workshop on
ER -
 
Said Hamdioui, Delft University of Technology
Georgi Gaydadjiev, Delft University of Technology
Ad J. van de Goor, Delft University of Technology
According to the International Technology Roadmap for Semiconductors (ITRS 2001), embedded memories will continue to dominate the increasing system on chips (SoCs) content in the next years, approaching 94% in about 10 years. Therefore the memory yield will have a dramatical impact on the overall defect-per-million (DPM) level, hence on the overall SoC yield. Meeting a high memory yield requires understanding memory designs, modelling their faulty behaviors in the presence of defects, designing adequate tests and diagnosis strategies as well as efficient repair schemes. This paper presents the state of art in memory testing including fault modeling, test design, Built-In-Self-Test (BIST) and Built-In-Self-Repair (BISR). Further research challenges and opportunities are discussed in enabling testing (embedded) memories, which use deep submicron technologies.
Citation:
Said Hamdioui, Georgi Gaydadjiev, Ad J. van de Goor, "The State-of-Art and Future Trends in Testing Embedded Memories," mtdt, pp.54-59, Records of the 2004 International Workshop on Memory Technology, Design and Testing (MTDT'04), 2004
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