A Novel Memory Array Based on an Annular Single-Poly EPROM Cell for Use in Standard CMOS Technology

M
MTDT
2002
The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002)
Abstract - A Novel Memory Array Based on an Annular Single-Poly EPROM Cell for Use in Standard CMOS Technology

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	Similar Articles Articles by Cyrille Dray Articles by Philippe Gendrier

The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002)

Isle of Bendor, France

July 10-July 12

ISBN: 0-7695-1617-3

	ASCII Text	x
	Cyrille Dray, Philippe Gendrier, "A Novel Memory Array Based on an Annular Single-Poly EPROM Cell for Use in Standard CMOS Technology," Memory Technology, Design and Testin, IEEE International Workshop on, pp. 143, The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002), 2002.

	BibTex	x
	@article{ 10.1109/MTDT.2002.1029775, author = {Cyrille Dray and Philippe Gendrier}, title = {A Novel Memory Array Based on an Annular Single-Poly EPROM Cell for Use in Standard CMOS Technology}, journal ={Memory Technology, Design and Testin, IEEE International Workshop on}, volume = {0}, year = {2002}, issn = {1087-4852}, pages = {143}, doi = {http://doi.ieeecomputersociety.org/10.1109/MTDT.2002.1029775}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Memory Technology, Design and Testin, IEEE International Workshop on TI - A Novel Memory Array Based on an Annular Single-Poly EPROM Cell for Use in Standard CMOS Technology SN - 1087-4852 SP EP A1 - Cyrille Dray, A1 - Philippe Gendrier, PY - 2002 KW - null VL - 0 JA - Memory Technology, Design and Testin, IEEE International Workshop on ER -

Cyrille Dray, STMicroelectronics

Philippe Gendrier, STMicroelectronics

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MTDT.2002.1029775

Within the scope of non-volatile memories, CMOS compatibility and portability are serious issues. We describe here an edgeless single-poly floating gate p-channel memory cell, which can be embedded into a novel memory array architecture. It features high electrical performance together with a robustness with respect to the process. It has been processed in a 0.18 ?m HCMOS technology from STMicroelectronics, Crolles.

Citation:

Cyrille Dray, Philippe Gendrier, "A Novel Memory Array Based on an Annular Single-Poly EPROM Cell for Use in Standard CMOS Technology," mtdt, pp.143, The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002), 2002

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