The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002) A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories Isle of Bendor, France July 10-July 12 ISBN: 0-7695-1617-3
We present a simulator for evaluating the redundancy analysis (RA) algorithms. The simulator can calculate the repair rate (the ratio of the number of repaired memories to the number of defective memories) of the given RA algorithm and the associated memory configuration and redundancy structure. With the tool, the user also can easily assess and plan the redundant (spare) elements, and subsequently develop the built-in redundancy analysis (BIRA) algorithms and circuits that are essential for built-in self-repair (BISR) of embedded memories. The simulator has another important feature — it can simulate the sequence of the detected faults in the real order, improving the accuracy of the analysis results.
Index Terms:
embedded memory, memory testing, memory repair, redundancy analysis, simulation
Citation:
Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu, "A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories," mtdt, pp.68, The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002), 2002 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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