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The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002)
Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems
Isle of Bendor, France
July 10-July 12
ISBN: 0-7695-1617-3
ASCII Text
x 
 
Luca Schiano, Cecilia Metra, Diego Marino, "Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems," Memory Technology, Design and Testin, IEEE International Workshop on, pp. 49, The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002), 2002.
 
 
BibTex
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@article{ 10.1109/MTDT.2002.1029763,
author = {Luca Schiano and Cecilia Metra and Diego Marino},
title = {Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems},
journal ={Memory Technology, Design and Testin, IEEE International Workshop on},
volume = {0},
year = {2002},
issn = {1087-4852},
pages = {49},
doi = {http://doi.ieeecomputersociety.org/10.1109/MTDT.2002.1029763},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Memory Technology, Design and Testin, IEEE International Workshop on
TI - Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems
SN - 1087-4852
SP
EP
A1 - Luca Schiano,
A1 - Cecilia Metra,
A1 - Diego Marino,
PY - 2002
KW - null
VL - 0
JA - Memory Technology, Design and Testin, IEEE International Workshop on
ER -
 
Luca Schiano, University of Bologna
Cecilia Metra, University of Bologna
Diego Marino, Alstom Transport Spa
We propose the self-checking design of the Transmission and Reception Blocks of a Trackside Control System used for railway applications. Our scheme has been conceived for Field-Programmable Gate Arrays. A prototype has been implemented, whose correct operation has been verified by means of post-layout simulations and experimental measurements. Our scheme negligibly impacts system?s performance and features self-checking ability with respect to a wide set of possible internal faults, representative of the most likely faults for FPGA-implemented systems.
Citation:
Luca Schiano, Cecilia Metra, Diego Marino, "Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems," mtdt, pp.49, The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002), 2002
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