This paper describes the use of Verilog HDL in a series of design projects for an undergraduate Computer Organization course. Students are given Verilog "working models" of pedagogical designs that can first be simulated to enhance initial learning and then extended and modified to develop more in-depth understanding. Projects include adder/ALU design and processor design using the single cycle, multicycle, and pipelined processor implementations presented in the popular Patterson & Hennessy text [1]. This incremental approach allows students to focus on the underlying concepts of the course as they become more familiar with Verilog. The models and supporting project assignments are available online at http://foghorn.cadlab.lafayette.edu/ece313/.