This paper describes the authors experience with teaching VHDL (and more recently, Verilog) to undergraduate and graduate students at WPI and to engineers through various short courses in industry. The courses have concentrated on logic synthesis targeting CPLDs and FPGAs. All the courses had a major lab component where students could use simulation tools to test their design using test benches and also synthesis tools to synthesize, implement, and download the configuration bit-stream to evaluation boards. The paper concentrates on some of the problems that students encounter when they are trying to design their digital systems using HDLs. In addition to the conceptual issues with using a language to describe hardware behavior, the newer higher capacity devices provide additional challenges as more functions, including embedded processors, are added to the device.