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5th International Conference on Microelectronics for Neural Networks and Fuzzy Systems (MicroNeuro '96)
VIP: An FPGA-based Processor for Image Processing and Neural Networks
Lausanne, SWITZERLAND
February 12-February 14
ISBN: 0-8186-7373-7
ASCII Text
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Jocelyn Cloutier, Steven Pigeon, Francois R. Boyer, Eric Cosatto, Patrice Y. Simard, "VIP: An FPGA-based Processor for Image Processing and Neural Networks," Microelectronics for Neural Networks and Fuzzy Systems, International Conference on/Microelectronics for Neural, Fuzzy, and Bio-Inspired Systems, International Conference on, pp. 330, 5th International Conference on Microelectronics for Neural Networks and Fuzzy Systems (MicroNeuro '96), 1996.
 
 
BibTex
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@article{ 10.1109/MNNFS.1996.493811,
author = {Jocelyn Cloutier and Steven Pigeon and Francois R. Boyer and Eric Cosatto and Patrice Y. Simard},
title = {VIP: An FPGA-based Processor for Image Processing and Neural Networks},
journal ={Microelectronics for Neural Networks and Fuzzy Systems, International Conference on/Microelectronics for Neural, Fuzzy, and Bio-Inspired Systems, International Conference on},
volume = {0},
year = {1996},
issn = {1086-1947},
pages = {330},
doi = {http://doi.ieeecomputersociety.org/10.1109/MNNFS.1996.493811},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Microelectronics for Neural Networks and Fuzzy Systems, International Conference on/Microelectronics for Neural, Fuzzy, and Bio-Inspired Systems, International Conference on
TI - VIP: An FPGA-based Processor for Image Processing and Neural Networks
SN - 1086-1947
SP
EP
A1 - Jocelyn Cloutier,
A1 - Steven Pigeon,
A1 - Francois R. Boyer,
A1 - Eric Cosatto,
A1 - Patrice Y. Simard,
PY - 1996
VL - 0
JA - Microelectronics for Neural Networks and Fuzzy Systems, International Conference on/Microelectronics for Neural, Fuzzy, and Bio-Inspired Systems, International Conference on
ER -
 
Jocelyn Cloutier, Universite de Montreal
Steven Pigeon, Universite de Montreal
Francois R. Boyer, Universite de Montreal
Eric Cosatto, AT&T Bell Laboratories
Patrice Y. Simard, AT&T Bell Laboratories
We present in this paper the architecture and implementation of the Virtual Image Processor (VIP) which is an SIMD multiprocessor build with large FPGAs. The SIMD architecture , together with a 2D torus connection topology, is well suited for image processing, pattern recognition and neural network algorithms. The VIP board can be programmed on-line at the logic level, allowing optimal hardware dedication to any given algorithm.
Citation:
Jocelyn Cloutier, Steven Pigeon, Francois R. Boyer, Eric Cosatto, Patrice Y. Simard, "VIP: An FPGA-based Processor for Image Processing and Neural Networks," microneuro, pp.330, 5th International Conference on Microelectronics for Neural Networks and Fuzzy Systems (MicroNeuro '96), 1996
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