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IBM Power Edge of Network Processor: A Wire-Speed System on a Chip
March/April 2011 (vol. 31 no. 2)
pp. 76-85
ASCII Text
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Jeffrey D. Brown, Sandra Woodward, Brian M. Bass, Charles L. Johnson, "IBM Power Edge of Network Processor: A Wire-Speed System on a Chip," IEEE Micro, vol. 31, no. 2, pp. 76-85, March/April, 2011.
 
 
BibTex
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@article{ 10.1109/MM.2011.3,
author = {Jeffrey D. Brown and Sandra Woodward and Brian M. Bass and Charles L. Johnson},
title = {IBM Power Edge of Network Processor: A Wire-Speed System on a Chip},
journal ={IEEE Micro},
volume = {31},
number = {2},
issn = {0272-1732},
year = {2011},
pages = {76-85},
doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2011.3},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - IBM Power Edge of Network Processor: A Wire-Speed System on a Chip
IS - 2
SN - 0272-1732
SP76
EP85
EPD - 76-85
A1 - Jeffrey D. Brown,
A1 - Sandra Woodward,
A1 - Brian M. Bass,
A1 - Charles L. Johnson,
PY - 2011
KW - Multicore multiprocessors
KW - single-chip multiprocessors
KW - on-chip interconnection networks
KW - parallel architectures
KW - processor architectures
KW - network-level security and protection
KW - data encryption
KW - support for multithreaded execution
KW - microarchitecture implementation considerations
VL - 31
JA - IEEE Micro
ER -
 

The IBM Power Edge of Network processor combines the attributes of a general-purpose processing subsystem with function accelerators and networking interfaces to create a system on a chip that's targeted for applications at the edge of network. This article discusses in detail the processing, accelerator, and network interface subsystems and explores applications well suited to the PowerEN processor.

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Index Terms:
Multicore multiprocessors, single-chip multiprocessors, on-chip interconnection networks, parallel architectures, processor architectures, network-level security and protection, data encryption, support for multithreaded execution, microarchitecture implementation considerations
Citation:
Jeffrey D. Brown, Sandra Woodward, Brian M. Bass, Charles L. Johnson, "IBM Power Edge of Network Processor: A Wire-Speed System on a Chip," IEEE Micro, vol. 31, no. 2, pp. 76-85, March-April 2011, doi:10.1109/MM.2011.3
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