Security Refresh: Protecting Phase-Change Memory against Malicious Wear Out January/February 2011 (vol. 31 no. 1) pp. 119-127
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2010.101
As dynamic RAM scaling approaches its physical limit, phase-change memory is the most mature and well-studied option for potential DRAM replacement. However, malicious wear-out attacks can exploit PCM's limited write endurance. To address this, a low-cost wear-leveling scheme can dynamically randomize the data addresses across the entire address space and obfuscate their actual locations from users and system software. 1. S. Cho and H. Lee, "Flip-N-Write: A Simple Deterministic Technique to Improve PRAM Write Performance, Energy and Endurance," Proc. IEEE/ACM Int'l Symp. Microarchitecture, ACM Press, 2009, pp. 347-357.
Index Terms:
phase change memory, security, wear leveling, dynamic address remapping
Citation:
Nak Hee Seong, Dong Hyuk Woo, Hsien-Hsin S. Lee, "Security Refresh: Protecting Phase-Change Memory against Malicious Wear Out," IEEE Micro, vol. 31, no. 1, pp. 119-127, Jan.-Feb. 2011, doi:10.1109/MM.2010.101 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||