Larrabee: A Many-Core x86 Architecture for Visual Computing January/February 2009 (vol. 29 no. 1) pp. 10-21
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2009.9
The Larrabee many-core visual computing architecture uses multiple in-order x86 cores augmented by wide vector processor units, together with some fixed-function logic. This increases the architecture's programmability as compared to standard GPUs. The article describes the Larrabee architecture, a software renderer optimized for it, and other highly parallel applications. The article analyzes performance through scalability studies based on real-world workloads. DOI of original article is available at: http://doi.acm.org/10.1145/1399504.1360617 1. J. Nickolls, I. Buck, and M. Garland, "Scalable Parallel Programming with CUDA," ACM Queue, vol. 6, no. 2, 2008, pp. 40-53.
Index Terms:
graphics architecture, many-core computing, real-time graphics, software rendering, throughput computing, visual computing, parallel processing, SIMD, GPGPU
Citation:
Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Pradeep Dubey, Stephen Junkins, Adam Lake, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, Michael Abrash, Jeremy Sugerman, Pat Hanrahan, "Larrabee: A Many-Core x86 Architecture for Visual Computing," IEEE Micro, vol. 29, no. 1, pp. 10-21, Jan./Feb. 2009, doi:10.1109/MM.2009.9 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||