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Express Virtual Channels with Capacitively Driven Global Links
July/August 2009 (vol. 29 no. 4)
pp. 48-61
ASCII Text
x 
 
Tushar Krishna, Amit Kumar, Li-Shiuan Peh, Jacob Postman, Patrick Chiang, Mattan Erez, "Express Virtual Channels with Capacitively Driven Global Links," IEEE Micro, vol. 29, no. 4, pp. 48-61, July/August, 2009.
 
 
BibTex
x
 
@article{ 10.1109/MM.2009.64,
author = {Tushar Krishna and Amit Kumar and Li-Shiuan Peh and Jacob Postman and Patrick Chiang and Mattan Erez},
title = {Express Virtual Channels with Capacitively Driven Global Links},
journal ={IEEE Micro},
volume = {29},
number = {4},
issn = {0272-1732},
year = {2009},
pages = {48-61},
doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2009.64},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - Express Virtual Channels with Capacitively Driven Global Links
IS - 4
SN - 0272-1732
SP48
EP61
EPD - 48-61
A1 - Tushar Krishna,
A1 - Amit Kumar,
A1 - Li-Shiuan Peh,
A1 - Jacob Postman,
A1 - Patrick Chiang,
A1 - Mattan Erez,
PY - 2009
KW - hardware
KW - networks on chip
KW - interconnect
KW - express virtual channels
VL - 29
JA - IEEE Micro
ER -
 
Tushar Krishna, Princeton University
Amit Kumar, Princeton University
Li-Shiuan Peh, Princeton University
Jacob Postman, Oregon State University
Patrick Chiang, Oregon State University
Mattan Erez, University of Texas at Austin

Networks on chip must deliver high bandwidth at low latencies while keeping within a tight power envelope. Using express virtual channels for flow control improves energy-delay throughput by letting packets bypass intermediate routers, but EVCs have key limitations. Nochi (NoC with hybrid interconnect) overcomes these limitations by transporting data payloads and control information on separate planes, optimized for bandwidth and latency respectively.

1. A. Kumar et al., "Express Virtual Channels: Towards the Ideal Interconnection Fabric," Proc. Int'l Symp. Computer Architecture (ISCA 07), ACM Press, 2007, pp. 150-161.
2. Y. Hoskote et al., "A 5-GHz Mesh Interconnect for a Teraflops Processor," IEEE Micro, vol. 27, no. 5, Sept./Oct. 2007, pp. 51-61.
3. H.-S. Wang, L.-S. Peh, and S. Malik, "Power-Driven Design of Router Microarchitectures in On-Chip Networks," Proc. Int'l Symp. Microarchitecture (Micro 03), IEEE CS Press, 2003, pp. 105-116.
4. M.-J.E. Lee, W. Dally, and P. Chiang, "Low-Power Area-Efficient High-Speed I/O Circuit Techniques," IEEE J. Solid-State Circuits, vol. 35, no. 11, Nov. 2000, pp. 1591-1591.
5. M.M.K. Martin et al., "Multifacet's General Execution-Driven Multiprocessor Simulator (GEMS) Toolset," SIGARCH Computer Architecture News, vol. 33, no. 4, 2005, pp. 92-99.
6. N. Agarwal et al., "Garnet: A Detailed On-Chip Network Model inside a Full-System Simulator," Proc. Int'l Symp. Performance Analysis of Systems and Software (ISPASS 09), IEEE CS Press, 2009, pp. 33-42.

Index Terms:
hardware, networks on chip, interconnect, express virtual channels
Citation:
Tushar Krishna, Amit Kumar, Li-Shiuan Peh, Jacob Postman, Patrick Chiang, Mattan Erez, "Express Virtual Channels with Capacitively Driven Global Links," IEEE Micro, vol. 29, no. 4, pp. 48-61, July/Aug. 2009, doi:10.1109/MM.2009.64
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