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IBM z10: The Next-Generation Mainframe Microprocessor
March/April 2008 (vol. 28 no. 2)
pp. 19-29
ASCII Text
x 
 
Charles F. Webb, "IBM z10: The Next-Generation Mainframe Microprocessor," IEEE Micro, vol. 28, no. 2, pp. 19-29, March/April, 2008.
 
 
BibTex
x
 
@article{ 10.1109/MM.2008.26,
author = {Charles F. Webb},
title = {IBM z10: The Next-Generation Mainframe Microprocessor},
journal ={IEEE Micro},
volume = {28},
number = {2},
issn = {0272-1732},
year = {2008},
pages = {19-29},
doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2008.26},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - IBM z10: The Next-Generation Mainframe Microprocessor
IS - 2
SN - 0272-1732
SP19
EP29
EPD - 19-29
A1 - Charles F. Webb,
PY - 2008
KW - Hot Chips 19
KW - microprocessor
KW - pipeline
KW - accelerators
KW - mainframe
KW - symmetric multiprocessor (SMP)
KW - branch prediction
KW - high-frequency design
KW - reliability
KW - decimal floating-point
VL - 28
JA - IEEE Micro
ER -
 
The IBM System z10 includes four microprocessor cores—each with a private 3-Mbyte cache—and integrated accelerators for decimal floating-point computation, cryptography, and data compression. A separate SMP hub chip provides a shared third-level cache and interconnect fabric for multiprocessor scaling. This article focuses on the high-frequency design techniques used to achieve a 4.4-GHz system, and on the pipeline design that optimizes z10's CPU performance.

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Index Terms:
Hot Chips 19, microprocessor, pipeline, accelerators, mainframe, symmetric multiprocessor (SMP), branch prediction, high-frequency design, reliability, decimal floating-point
Citation:
Charles F. Webb, "IBM z10: The Next-Generation Mainframe Microprocessor," IEEE Micro, vol. 28, no. 2, pp. 19-29, Mar./Apr. 2008, doi:10.1109/MM.2008.26
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