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Architecting Efficient Interconnects for Large Caches with CACTI 6.0
January/February 2008 (vol. 28 no. 1)
pp. 69-79
ASCII Text
x 
 
Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi, "Architecting Efficient Interconnects for Large Caches with CACTI 6.0," IEEE Micro, vol. 28, no. 1, pp. 69-79, January/February, 2008.
 
 
BibTex
x
 
@article{ 10.1109/MM.2008.2,
author = {Naveen Muralimanohar and Rajeev Balasubramonian and Norman P. Jouppi},
title = {Architecting Efficient Interconnects for Large Caches with CACTI 6.0},
journal ={IEEE Micro},
volume = {28},
number = {1},
issn = {0272-1732},
year = {2008},
pages = {69-79},
doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2008.2},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - Architecting Efficient Interconnects for Large Caches with CACTI 6.0
IS - 1
SN - 0272-1732
SP69
EP79
EPD - 69-79
A1 - Naveen Muralimanohar,
A1 - Rajeev Balasubramonian,
A1 - Norman P. Jouppi,
PY - 2008
KW - on-chip interconnects
KW - CACTI 6.0
KW - cache design
VL - 28
JA - IEEE Micro
ER -
 
Naveen Muralimanohar, University of Utah
Rajeev Balasubramonian, University of Utah
Norman P. Jouppi, Hewlett-Packard Laboratories
Interconnects play an increasingly important role in determining the power and performance characteristics of modern processors. An enhanced version of the popular CACTI tool primarily focuses on interconnect design for large scalable caches. The new version can help evaluate novel interconnection networks for cache access and accurately estimate the delay, power, and area of large caches with uniform and nonuniform access times.

1. 69 N. Muralimanohar and R. Balasubramonian, "Interconnect Design Considerations for Large NUCA Caches," Proc. 34th Int'l Symp. Computer Architecture (ISCA 07), ACM Press, 2007, pp. 369-380.2. N. Muralimanohar, R. Balasubramonian, and N.P. Jouppi, "Optimizing NUCA Organizations and Wiring Alternatives for Large Caches With CACTI 6.0," Proc. 40th Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO 07), IEEE CS Press, 2007, pp. 3-14.3. S. Thoziyoor, N. Muralimanohar, and N. Jouppi, "CACTI 5.0," tech. report HPL-2007-167, HP Lab., 2007.4. C. Kim, D. Burger, and S. Keckler, "An Adaptive, Non-Uniform Cache Structure for Wire-Dominated On-Chip Caches," Proc. 10th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS 02), ACM Press, 2002, pp. 211-222.5. W. Dally and B. Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann, 2003.6. R. Mullins, A. West, and S. Moore, "Low-Latency Virtual-Channel Routers for On-Chip Networks," Proc. 31st Int'l Symp. Computer Architecture (ISCA 04), IEEE CS Press, 2004, p. 188.7. L.-S Peh and W. Dally, "A Delay Model and Speculative Architecture for Pipelined Routers," Proc. 7th IEEE Symp. High-Performance Computer Architecture (HPCA 01), IEEE CS Press, 2001, p. 255.8. R. Kumar, V. Zyuban, and D. Tullsen, "Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads, and Scaling," Proc. 32nd Ann. Int'l Symp. Computer Architecture (ISCA 05), IEEE CS Press, 2005, pp. 408-419.

Index Terms:
on-chip interconnects, CACTI 6.0, cache design
Citation:
Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi, "Architecting Efficient Interconnects for Large Caches with CACTI 6.0," IEEE Micro, vol. 28, no. 1, pp. 69-79, Jan./Feb. 2008, doi:10.1109/MM.2008.2
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